Accurate reference spur estimation using behavioural modelling

Abstract

Reference spur is a periodic noise that can be observed at the output of an integer-N phase-locked loop (PLL). This noise is dominated by circuit non-idealities in phase/frequency detector (PFD) and charge pump. The spur magnitude is linearly related with Voltage Controlled Oscillator (VCO) gain. Estimating this noise using transistor level simulation is time consuming. Therefore, in this paper we present a Simulink behavioural model to accurately estimate the reference spur. PFD delay, charge pump current mismatch, rise and fall times effect and switching delay, in addition to non-linearity in the VCO gain, are all included in this model. The proposed model was used to estimate the reference spur for an 18.5 GHz PLL and the results were compared with transistor level simulation, and show less than 3% difference in the result.