Design and implementation of a GaAs systolic floating-point processing element

Abstract

The design and layout of a prototype single precision systolic floating-point processing element (PE) is described. It is intended for use in a class of systolic array processors which perform matrix computations. Each PE is constructed from a digit-serial systolic ring of four programmable cells and performs floating-point multiplication and accumulation. A single PE has been fabricated in a 0.8 μm gallium arsenide E/D MESFET process and has a maximum clock speed of 300 MHz. The chip can be configured into a 16×16 array to achieve a peak computation rate of 2.5 GFLOPS.