Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/100193
Type: Theses
Title: Subthreshold and near-threshold techniques for ultra-low power CMOS design
Author: Kitchener, James Anthony
Issue Date: 2015
School/Discipline: School of Electrical and Electronic Engineering
Abstract: The miniaturisation of electronic circuits allows the potential for new applications, such as smart-dust or the Internet of Things. However, the design of batteries has not improved at the same rate as CMOS technology, so circuits need to be designed for improved energy efficiency to enable new form factors and applications. To address these issues, the use of subthreshold and near-threshold supply voltages is proposed. Throughout this thesis, the nature of what makes a design suitable for subthreshold use is examined. This work starts at the gate level, where the effects of transistor geometry and valency are examined. The levels of abstraction are progressively increased until high level architectures are considered, where quasi- delay-insensitive and globally-asynchronous locally-synchronous designs are argued as suitable for designing reliable systems. To assist in this, a methodology for partitioning systems into separate timing domains is proposed, and applied to published designs. The underlying theme throughout the exploration of subthreshold technology is the effects and mitigation of process and environmental variation, to which designs are increasingly susceptible as the supply voltage is lowered. This vulnerability affects all levels of design, from the widths of individual transistor to the choice of overall architectures, where a fundamental issue is the ability to determine when a unit of work has been performed. Not all applications respond well to the scaling of supply voltage. To address this, an alternative approach is considered where the system spends much of its lifetime in a powered-down state, being woken at appropriate intervals by a wakeup timer. As power consumption is a function of frequency, this timer seeks to achieve energy efficiency by maximising the period of oscillation. Despite the higher supply voltages considered, the themes of environmental and process variation continue, as the wakeup timers examined share similarities to subthreshold designs. Two of the proposed timers have been fabricated and are compared to simulated results and other published work.
Advisor: Phillips, Braden Jace
Liebelt, Michael J.
Dissertation Note: Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2015.
Keywords: subthreshold
near-threshold
CMOS
asynchronous
oscillator
wakeup
GALS
globally asynchronous locally synchronous
Provenance: This electronic version is made publicly available by the University of Adelaide in accordance with its open access policy for student theses. Copyright in this thesis remains with the author. This thesis may incorporate third party material which has been used by the author pursuant to Fair Dealing exceptions. If you are the owner of any included third party copyright material you wish to be removed from this electronic version, please complete the take down form located at: http://www.adelaide.edu.au/legals
Appears in Collections:Research Theses

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