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|Title:||Few electron limit of n-type metal oxide semiconductor single electron transistors|
De Michielis, M.
|Citation:||Nanotechnology, 2012; 23(21):215204-1-215204-5|
|Enrico Prati, Marco De Michielis, Matteo Belli, Simone Cocco, Marco Fanciulli, Dharmraj Kotekar-Patil, Matthias Ruoff, Dieter P Kern, David A Wharam, Jan Verduijn, Giuseppe C Tettamanzi, Sven Rogge, Benoit Roche, Romain Wacquez, Xavier Jehl, Maud Vinet and Marc Sanquer|
|Abstract:||We report the electronic transport on n-type silicon single electron transistors (SETs) fabricated in complementary metal oxide semiconductor (CMOS) technology. The n-type metal oxide silicon SETs (n-MOSSETs) are built within a pre-industrial fully depleted silicon on insulator (FDSOI) technology with a silicon thickness down to 10 nm on 200 mm wafers. The nominal channel size of 20 × 20 nm(2) is obtained by employing electron beam lithography for active and gate level patterning. The Coulomb blockade stability diagram is precisely resolved at 4.2 K and it exhibits large addition energies of tens of meV. The confinement of the electrons in the quantum dot has been modeled by using a current spin density functional theory (CS-DFT) method. CMOS technology enables massive production of SETs for ultimate nanoelectronic and quantum variable based devices.|
|Rights:||© 2012 IOP Publishing Ltd Printed in the UK & the USA|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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