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dc.contributor.advisorLiebelt, Michael J.-
dc.contributor.authorApisake, Hongwitayakorn-
dc.subjectCache memory -- Evaluation; Operating systems (Computers); RISC microprocessors; Reduced instruction set computersen
dc.titleThe study of trace cache memory on superscalar DLX processoren
dc.contributor.schoolDept. of Electrical and Electronic Engineeringen
dc.provenanceThis electronic version is made publicly available by the University of Adelaide in accordance with its open access policy for student theses. Copyright in this thesis remains with the author. This thesis may incorporate third party material which has been used by the author pursuant to Fair Dealing exceptions. If you are the owner of any included third party copyright material you wish to be removed from this electronic version, please complete the take down form located at:
dc.description.dissertationThesis (M.Eng.Sc.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 2003.en
Appears in Collections:Research Theses

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