The implementation of the testability strategies in a VLSI circuit

Abstract

The Transform and Filter Brick (TFB) is a 200,000 transistor, CMOS, program controlled, highly interconnected, parallel arithmetic processor for digital signal processing applications. The chip design has been carried out by a group of postgraduate students of the Department of Electrical and Electronic Engineering at Adelaide University. The architecture and its component modules and control were specified in terms of required function, performance and interfacing by the author in collaboration with Alex Dickinson, and the results are embodied in the TFB system specification document. As well as maintaining a consultative and coordinational role with regard to the system architecture, the author has been solely responsible for the testability of the chip. A survey of current methodologies, theories and practices in the field of VLSI testing was carried out, with a view to establishing their applicability or otherwise to the design of the TFB chip. A review of this body of literature is included herein. As a result of this survey, the decisior was taken to address the testability problems of the chip using some of these "Design for Test" techniques. Some initial investigations were made into including a totally built-in test system for the control RAM array, but this was put aside in favour of a more global approach to the testing problem, based or scan paths throughout critical areas of the chip. The final system, both the on-chip hardware and the externally applied test program, is specified in this work.