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Type: Conference paper
Title: Memory-efficient hierarchical neural architecture search for image denoising
Author: Zhang, H.
Li, Y.
Chen, H.
Shen, C.
Citation: Proceedings / CVPR, IEEE Computer Society Conference on Computer Vision and Pattern Recognition. IEEE Computer Society Conference on Computer Vision and Pattern Recognition, 2020, pp.3654-3663
Publisher: IEEE
Issue Date: 2020
Series/Report no.: IEEE Conference on Computer Vision and Pattern Recognition
ISSN: 1063-6919
Conference Name: IEEE Conference on Computer Vision and Pattern Recognition (14 Jun 2020 - 19 Jun 2020 : virtual online)
Statement of
Haokui Zhang, Ying Li, Hao Chen, Chunhua Shen
Abstract: Recently, neural architecture search (NAS) methods have attracted much attention and outperformed manually designed architectures on a few high-level vision tasks. In this paper, we propose HiNAS (Hierarchical NAS), an effort towards employing NAS to automatically design effective neural network architectures for image denoising. Hi- NAS adopts gradient based search strategies and employs operations with adaptive receptive field to build an flexible hierarchical search space. During the search stage, HiNAS shares cells across different feature levels to save memory and employ an early stopping strategy to avoid the collapse issue in NAS, and considerably accelerate the search speed. The proposed HiNAS is both memory and computation efficient, which takes only about 4.5 hours for searching using a single GPU. We evaluate the effectiveness of our proposed HiNAS on two different datasets, namely an additive white Gaussian noise dataset BSD500, and a realistic noise dataset SIM1800. Experimental results show that the architecture found by HiNAS has fewer parameters and enjoys a faster inference speed, while achieving highly competitive performance compared with state-of-the-art methods. We also present analysis on the architectures found by NAS. HiNAS also shows good performance on experiments for image de-raining.
Description: Published 05 August 2020
Rights: © 2020 IEEE
DOI: 10.1109/CVPR42600.2020.00371
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