Investigation of critical slowing down in a bistable S-SEED

Abstract

A simulation of S-SEED switching based upon experimental data is developed that includes the effect of critical slowing down. The simulation's accuracy is demonstrated by close agreement with the results from experimental S-SEED switching. The simulation is subsequently used to understand how the phenomenon of critical slowing down applies to switching of an S-SEED and how the effect on photonic analog-to-digital (A/D) converter performance may be minimized.