Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/19718
Type: Thesis
Title: Design and evaluation of a memory architecture for a parallel matrix processor array / Nicholas M. Betts.
Author: Betts, Nicholas M.
Issue Date: 2000
School/Discipline: Dept. of Electrical and Electronic Engineering
Advisory Centre for University Education
Abstract: Proposes a specialized matrix processor architecture that targets numerically intensive algorithms that can be cast in matrix terms.
Dissertation Note: Thesis (Ph.D.) - -University of Adelaide, Dept. of Electrical and Electronic Engineering, 2000
Subject: Matrices Data processing.
Computer algorithms.
Parallel processing (Electronic computers)
Description: CD-ROM in pocket on back end paper.
Bibliography: leaves 254-259.
xiv, 259 leaves : ill. ; 30 cm + 1 computer optical disc (4 3/4 in.)
Provenance: This electronic version is made publicly available by the University of Adelaide in accordance with its open access policy for student theses. Copyright in this thesis remains with the author. This thesis may incorporate third party material which has been used by the author pursuant to Fair Dealing exception. If you are the author of this thesis and do not wish it to be made publicly available or If you are the owner of any included third party copyright material you wish to be removed from this electronic version, please complete the take down form located at: http://www.adelaide.edu.au/legals
Appears in Collections:Research Theses

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