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Type: Thesis
Title: MatRISC : a RISC multiprocessor for matrix applications / Andrew James Beaumont-Smith.
Author: Beaumont-Smith, Andrew James
Issue Date: 2001
School/Discipline: Dept. of Electrical and Electronic Engineering
Abstract: This thesis proposes a highly integrated SOC (system on a chip) matrix-based parallel processor which can be used as a co-processor when integrated into the on-chip cache memory of a microprocessor in a workstation environment.
Dissertation Note: Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 2002
Subject: Reduced instruction set computers.
Cache memory Evaluation.
Operating systems (Computers)
Description: "November, 2001"
Errata on back page.
Includes bibliographical references (p. 179-183)
xxii, 193 p. : ill. (some col.), plates (col.) ; 30 cm.
Provenance: This electronic version is made publicly available by the University of Adelaide in accordance with its open access policy for student theses. Copyright in this thesis remains with the author. This thesis may incorporate third party material which has been used by the author pursuant to Fair Dealing exception. If you are the author of this thesis and do not wish it to be made publicly available or If you are the owner of any included third party copyright material you wish to be removed from this electronic version, please complete the take down form located at:
Appears in Collections:Research Theses

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