Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/22858
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Type: Journal article
Title: Fast decimal floating-point division
Author: Nikmehr, H.
Phillips, B.
Lim, C.
Citation: IEEE Transactions on Very Large Scale Integration Systems, 2006; 14(9):951-961
Publisher: IEEE-Inst Electrical Electronics Engineers Inc
Issue Date: 2006
ISSN: 1063-8210
1557-9999
Statement of
Responsibility: 
Hooman Nikmehr, Braden Phillips and Cheng-Chew Lim
Abstract: A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature
Keywords: Binary-coded decimal (BCD)
decimal floating-point (DFP) arithmetic
digit recurrence division
Rights: Copyright © 2006 IEEE
DOI: 10.1109/TVLSI.2006.884047
Appears in Collections:Aurora harvest 6
Electrical and Electronic Engineering publications

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