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|Title:||A VSLI chip implementation of an A/D converter error table compensator|
|Citation:||Computer Standards and Interfaces, 2001; 23(2):111-122|
|Publisher:||Elsevier Science BV|
|A. Beaumont-Smith, J. Tsimbinos, C. C. Lim and W. Marwood|
|Abstract:||Error table compensation can be used to improve the spurious free dynamic range performance of high speed A/D converters. This paper gives details of an error table compensator system that uses a VLSI chip incorporating a transversal filter programmed as a wideband differentiator, additional on-chip circuits including delays and an adder, and a lookup table that is stored in external memory. The cascadable 10GOPS transversal filter differentiator chip has been designed and fabricated and can operate in 32-tap symmetric, 32-tap anti-symmetric or 16-tap non-symmetric modes. It has programmable tap weights and uses 16-bit signed arithmetic with radix-16 multipliers and 4-2 compressors to reduce the transistor count. The chip was fabricated in a 0.35-μm CMOS process, measures 3.1 × 4.4 mm and contains 310,000 transistors. The chip is pipelined and has a maximum clock rate of 200 MHz. It is shown that the error table compensation system is capable of providing between 7 and 13 dB improvement in the dynamic range of typical high-speed A/D converters. © 2001 Elsevier Science B.V. All rights reserved.|
|Description:||Copyright © 2001 Elsevier Science|
|Appears in Collections:||Aurora harvest 2|
Electrical and Electronic Engineering publications
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