Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/2335
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Type: Journal article
Title: Low power serial-parallel dynamic shift register
Author: Lee, L.
Al-Sarawi, S.
Abbott, D.
Citation: Electronics Letters, 2003; 39(1):19-20
Publisher: IEE-Inst Elec Eng
Issue Date: 2003
ISSN: 0013-5194
Statement of
Responsibility: 
L. Lee, S. Al-Sarawi and D. Abbott
Abstract: Serial-to-parallel shift registers have a wide range of applications. These registers are commonly found in communication systems and interfaces between electronic peripherals. Presented is a unique low power area efficient 128 bit serial-to-parallel shift register design that contains only four transistors per stage. The new register uses the capacitive bootstrapping technique to overcome the threshold voltage drop of MOSFETs. This logic family is named non-ratioed bootstrap logic (NRBL). Target applications arc dense smart sensor arrays and image sensors.
Description: © 2003 Institution of Engineering and Technology
RMID: 0020030767
DOI: 10.1049/el:20030056
Appears in Collections:Electrical and Electronic Engineering publications

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