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Type: Journal article
Title: Compact parallel (m,n) counters based on self-timed threshold logic
Author: Celinski, P.
Lopez, J.
Al-Sarawi, S.
Abbott, D.
Citation: Electronics Letters, 2002; 38(13):633-635
Publisher: IEE-Inst Elec Eng
Issue Date: 2002
ISSN: 0013-5194
Statement of
Celinski, P. Lopez, J.F. Al-Sarawi, S. and Abbott, D.
Abstract: A new, highly compact implementation of general parallel counters (i.e. population counters) with logic depth 2, based on self-timed threshold logic, is presented. The novel feature of the design is the sharing among all threshold gates of a single capacitive network for computing the weighted sum of all input bits. The significance of the result is the reduction by almost 50% in the required number of capacitors. Interconnect routing cost is also reduced, resulting in significantly decreased total area
Description: © 2002 Institution of Engineering and Technology
RMID: 0020020200
DOI: 10.1049/el:20020438
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Appears in Collections:Electrical and Electronic Engineering publications

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