Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/2340
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Type: Journal article
Title: Low power, high speed, charge recycling CMOS threshold logic gate
Author: Celinski, P.
Lopez, J.
Al-Sarawi, S.
Abbott, D.
Citation: Electronics Letters, 2001; 37(17):1067-1069
Publisher: IEE-Inst Elec Eng
Issue Date: 2001
ISSN: 0013-5194
Statement of
Responsibility: 
Celinski, P.; Lopez, J.F.; Al-Sarawi, S. and Abbott, D.
Abstract: A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.
Description: © 2001 Institution of Engineering and Technology
RMID: 0020010229
DOI: 10.1049/el:20010742
Published version: http://scitation.aip.org/getabs/servlet/GetabsServlet?prog=normal&id=ELLEAK000037000017001067000001&idtype=cvips&gifs=Yes
Appears in Collections:Electrical and Electronic Engineering publications

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