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|Title:||Low power, high speed, charge recycling CMOS threshold logic gate|
|Citation:||Electronics Letters, 2001; 37(17):1067-1069|
|Publisher:||IEE-Inst Elec Eng|
|Celinski, P.; Lopez, J.F.; Al-Sarawi, S. and Abbott, D.|
|Abstract:||A new implementation of a threshold gate based on a capacitive input, charge recycling differential sense amplifier latch is presented. Simulation results indicate that the proposed structure has very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations, and is therefore highly suitable as an element in digital integrated circuit design.|
|Description:||© 2001 Institution of Engineering and Technology|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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