Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/2364
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Type: Journal article
Title: GaAs pseudodynamic latched logic for high performance processor cores
Author: Lopez, J.
Eshraghian, K.
Sarmiento, R.
Nunez, A.
Abbott, D.
Citation: IEEE Journal of Solid-State Circuits, 1997; 32(8):1297-1303
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date: 1997
ISSN: 0018-9200
Abstract: Email Print Request Permissions Save to Project A novel GaAs logic family, pseudodynamic latched logic (PDLL), is presented in this paper. It is composed of a dynamic circuit where the logic is performed and a static latch whose function is to permanently refresh the stored data on a dynamic node. Because of this hybrid structure, PDLL takes advantage of both static and dynamic families and thus, permits implementation of very complex structures with good speed-area power tradeoff. Moreover, the inclusion of the latch permits this class of logic family to be highly efficient for pipelined systems working even at high temperature without loss of data due to leakage currents. Barrel-shifters, programmable logic arrays (PLA's), and carry lookahead adders (CLA's) were verified by simulations demonstrating its feasibility for the development of high-performance very large scale integration (VLSI) systems
RMID: 0030006598
DOI: 10.1109/4.604094
Appears in Collections:Electrical and Electronic Engineering publications

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