Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/2446
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Type: Journal article
Title: Low depth, low power carry lookahead adders using threshold logic
Author: Celinski, P.
Lopez, J.
Al-Sarawi, S.
Abbott, D.
Citation: Microelectronics Journal, 2002; 33(12):1071-1077
Publisher: Elsevier Sci Ltd
Issue Date: 2002
ISSN: 0026-2692
Statement of
Responsibility: 
Peter Celinski, Jose F. López, S. Al-Sarawi and Derek Abbott
Abstract: This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.
RMID: 0020021170
DOI: 10.1016/S0026-2692(02)00112-X
Description (link): http://www.elsevier.com/wps/find/journaldescription.cws_home/405904/description#description
Appears in Collections:Electrical and Electronic Engineering publications

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