Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/28348
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Type: Conference paper
Title: Improved heuristics for optimal parallel multiplier synthesis
Author: Townsend, T.
Liebelt, M.
Citation: Proceedings of SPIE. Design, characterization, and packaging for MEMS and microelectronics II; 17-19 December, 2001 / Paul D. Franzon, Ajay P. Malshe, Francis E. Tay (eds.): v. 4593, pp. 209-219
Publisher: THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS
Publisher Place: USA
Issue Date: 2001
Series/Report no.: PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)
ISBN: 0819443239
ISSN: 0277-786X
Conference Name: Design, Characterization, and Packaging for MEMS and Microelectronics II (2001 : Adelaide, Australia)
Editor: Franzon, P.
Statement of
Responsibility: 
Townsend, Troy and Liebelt, Michael
Abstract: Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most area-efficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al.) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden.
Keywords: Multiplier design
partial product reduction tree
tree multiplier
column compression
heuristics
algorithms
circuit design
Description: © 2001 SPIE--The International Society for Optical Engineering
DOI: 10.1117/12.448852
Appears in Collections:Aurora harvest 6
Electrical and Electronic Engineering publications
Environment Institute publications

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