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|Title:||Improved heuristics for optimal parallel multiplier synthesis|
|Citation:||Proceedings of SPIE. Design, characterization, and packaging for MEMS and microelectronics II; 17-19 December, 2001 / Paul D. Franzon, Ajay P. Malshe, Francis E. Tay (eds.): v. 4593, pp. 209-219|
|Publisher:||THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS|
|Series/Report no.:||PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)|
|Conference Name:||Design, Characterization, and Packaging for MEMS and Microelectronics II (2001 : Adelaide, Australia)|
|Townsend, Troy and Liebelt, Michael|
|Abstract:||Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most area-efficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al.) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden.|
|Keywords:||Multiplier design; partial product reduction tree; tree multiplier; column compression; heuristics; algorithms; circuit design|
|Description:||© 2001 SPIE--The International Society for Optical Engineering|
|Appears in Collections:||Environment Institute publications|
Electrical and Electronic Engineering publications
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