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https://hdl.handle.net/2440/28348
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DC Field | Value | Language |
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dc.contributor.author | Townsend, T. | - |
dc.contributor.author | Liebelt, M. | - |
dc.contributor.editor | Franzon, P. | - |
dc.date.issued | 2001 | - |
dc.identifier.citation | Proceedings of SPIE. Design, characterization, and packaging for MEMS and microelectronics II; 17-19 December, 2001 / Paul D. Franzon, Ajay P. Malshe, Francis E. Tay (eds.): v. 4593, pp. 209-219 | - |
dc.identifier.isbn | 0819443239 | - |
dc.identifier.issn | 0277-786X | - |
dc.identifier.uri | http://hdl.handle.net/2440/28348 | - |
dc.description | © 2001 SPIE--The International Society for Optical Engineering | - |
dc.description.abstract | Parallel multipliers are of increasing importance for VLSI design, largely driven by the significant increase in demand for computer graphics and digital signal processing. The fastest (and, when pipelined, most area-efficient) multiplier class is partial product reduction tree (PPRT) based multipliers. The previous best known heuristic for PPRT design (published by Stelling et al.) is capable of producing the fastest possible circuits but suffers an infeasible computational burden. This paper introduces some results which significantly reduce the search space of this heuristic. Consequently, the speed of netlist generation is increased, and the circuits generated retain optimal performance. In addition, larger optimal multipliers may be synthesised due to the easing of the computational burden. | - |
dc.description.statementofresponsibility | Townsend, Troy and Liebelt, Michael | - |
dc.language.iso | en | - |
dc.publisher | THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS | - |
dc.relation.ispartofseries | PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE) | - |
dc.source.uri | http://dx.doi.org/10.1117/12.448852 | - |
dc.subject | Multiplier design | - |
dc.subject | partial product reduction tree | - |
dc.subject | tree multiplier | - |
dc.subject | column compression | - |
dc.subject | heuristics | - |
dc.subject | algorithms | - |
dc.subject | circuit design | - |
dc.title | Improved heuristics for optimal parallel multiplier synthesis | - |
dc.type | Conference paper | - |
dc.contributor.conference | Design, Characterization, and Packaging for MEMS and Microelectronics II (2001 : Adelaide, Australia) | - |
dc.identifier.doi | 10.1117/12.448852 | - |
dc.publisher.place | USA | - |
pubs.publication-status | Published | - |
dc.identifier.orcid | Liebelt, M. [0000-0001-6610-2876] | - |
Appears in Collections: | Aurora harvest 6 Electrical and Electronic Engineering publications Environment Institute publications |
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