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Type: Conference paper
Title: New efficient offset voltage cancellation techniques using digital trimming
Author: Al-Sarawi, S.
Citation: VLSI circuits and systems / José Fco. López, Juan A. Montiel-Nelson, Dimitris Pavlidis (eds.), pp. 65-76
Publisher: SPIE
Publisher Place: USA
Issue Date: 2003
Series/Report no.: Proceedings of SPIE--the International Society for Optical Engineering ; 5117.
ISBN: 0819449776
ISSN: 0277-786X
Conference Name: VLSI Circuits and Systems Conference (2003 : Gran Canaria, Spain)
Editor: Lopez, J.
Montiel Nelson, J.
Pavlidis, D.
Abstract: Operational amplifiers have an important role as a basic building block in analog circuit design. One of the performance limitations of these circuits is the input referred offset voltage or simply input offset voltage. This voltage can range between 1 - 30 mV depending on the fabrication process and the sizes of the ideally symmetrical input transistors of the differential amplifier. Two new techniques to digitally trim the offset voltage of operation amplifier are presented and discussed. The techniques can be divided into two categories. The first is called weighted current technique, while the second is called weighted voltage technique. The attractive features of the new techniques are the trimming is performed digitally, large dynamic range; require small silicon area, and the ability to provide auto-zero cancellation using extra hardware. In the presented analysis, a binary weighted scheme will be used. However, the techniques are not restricted to that scheme and they are still applicable with other weighting schemes. A detailed analysis of these techniques will be presented and discussed and measurement from fabrication and simulation will be presented.
Rights: ©2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
DOI: 10.1117/12.498597
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Electrical and Electronic Engineering publications

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