Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/28421
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Type: Conference paper
Title: State-of-the-art in CMOS threshold-logic VLSI gate implementations and applications
Author: Celinski, P.
Cotofana, S.
Lopez, J.
Al-Sarawi, S.
Abbott, D.
Citation: VLSI circuits and systems : 19-21 May 2003, Maspalomas, Gran Canaria, Spain / José Fco. López, Juan A. Montiel-Nelson, Dimitris Pavlidis (eds.), pp. 53-64
Publisher: SPIE
Publisher Place: USA
Issue Date: 2003
Series/Report no.: PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)
ISBN: 0819449776
ISSN: 0277-786X
Conference Name: VLSI Circuits and Systems Conference (2003 : Gran Canaria, Spain)
Statement of
Responsibility: 
Peter Celinski, Sorin D. Cotofana, Jose F. Lopez, Said F. Al-Sarawi, and Derek Abbott
Abstract: In recent years, there has been renewed interest in Threshold Logic(TL), mainly as a result of the development of a number ofsuccessful implementations of TL gates in CMOS. This paper presentsa summary of the recent developments in TL circuit design.High-performance TL gate circuit implementations are compared, and anumber of their applications in computer arithmetic operations arereviewed. It is shown that the application of TL in computerarithmetic circuit design can yield designs with significantlyreduced transistor count and area while at the same time reducingcircuit delay and power dissipation when compared to conventional CMOS logic.
Description: © 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
RMID: 0020032178
DOI: 10.1117/12.497792
Appears in Collections:Electrical and Electronic Engineering publications

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