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|Title:||A fast radix-4 floating-point divider with quotient digit selection by comparison multiples|
|Citation:||Computer Journal, 2007; 50(1):81-92|
|Publisher:||Oxford Univ Press|
|Hooman Nikmehr, Braden Phillips and Cheng-Chew Lim|
|Abstract:||A new implementation for minimally redundant radix-4 SRT division with the recurrence in the signed-digit format is introduced. The implementation is developed based on the comparison multiples idea. In the proposed approach, the quotient digit's magnitude is calculated by comparing the truncated partial remainder with two limited precision multiples of the divisor. The sign is determined by investigating the polarity of the truncated partial remainder. A timing evaluation using logical synthesis shows a latency of 2.34 ns for the recurrence of the proposed divider. It is 22% less than the conventional implementation.|
|Keywords:||SRT division; floating-point arthimetic; reduction addition|
|Rights:||© The Author 2006. Published by Oxford University Press on behalf of The British Computer Society.|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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