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|Title:||Parallel prefix adder design|
|Citation:||Proceedings of the 15th IEEE Smyposium on Computer Arithmetic, Vail, Colorado, 2001 : pp. 218-225.|
|Publisher:||IEEE - Institute of Electrical and Electronics Engineers|
|Series/Report no.:||PROCEEDINGS/SYMPOSIUM ON COMPUTER ARITHMETIC|
|Conference Name:||Symposium on Computer Arithmetic (15th : 2001 : Vail, Colorado)|
|Beaumont-Smith, A. ; Lim, C.-C.|
|Abstract:||The paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0.25 μm CMOS technology for a range of adder widths as a comparative study.|
|Rights:||© 2001 IEEE|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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