Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/40398
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Type: Conference paper
Title: Parallel prefix adder design
Author: BeaumontSmith, A.
Lim, C.C.
Citation: Proceedings of the 15th IEEE Smyposium on Computer Arithmetic, Vail, Colorado, 2001 : pp. 218-225.
Publisher: IEEE - Institute of Electrical and Electronics Engineers
Issue Date: 2001
Series/Report no.: PROCEEDINGS/SYMPOSIUM ON COMPUTER ARITHMETIC
ISBN: 0769511503
ISSN: 1063-6889
Conference Name: Symposium on Computer Arithmetic (15th : 2001 : Vail, Colorado)
Statement of
Responsibility: 
Beaumont-Smith, A. ; Lim, C.-C.
Abstract: The paper introduces two innovations in the design of prefix adder carry trees: use of high-valency prefix cells to achieve low logical depth and end-around carry adders with reduced fan-out loading (compared with the carry select and flagged prefix adders). An algorithm for generating parallel prefix carry trees suitable for use in a VLSI synthesis tool is presented with variable parameters including carry tree width, prefix cell valency, and the spacing of repeated carry trees. The area-delay design space is mapped for a 0.25 μm CMOS technology for a range of adder widths as a comparative study.
Rights: © 2001 IEEE
RMID: 0020074606
DOI: 10.1109/ARITH.2001.930122
Appears in Collections:Electrical and Electronic Engineering publications

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