Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/49685
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Type: | Conference paper |
Title: | Using genetic evolutionary software application testing to verify a DSP SoC |
Author: | Cheng, A. Lim, C. Sun, Y. He, H. Zhou, Z. Lei, T. |
Citation: | Proceedings of DELTA 2008, 4th IEEE International Symposium on Electronic Design, Test & Applications, 23-25 January, 2008: pp.20-25 |
Publisher: | IEEE |
Publisher Place: | USA |
Issue Date: | 2008 |
ISBN: | 0769531105 9780769531106 |
Conference Name: | IEEE International Symposium on Electronic Design (4th : 2008 : Hong Kong) |
Editor: | Osseiran, A. |
Statement of Responsibility: | Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei |
Abstract: | A digital signal processor (DSP) system-on-chip (SoC) can be designed using a variety of architectures and techniques. This often presents different verification challenges compared to conventional SoC or processor designs. Verification of such designs should take into account the goals and applications of the DSP, and how they are eventually used. This paper proposes an application based verification methodology and demonstrates this technique on a real-life DSP SoC design. Our technique employs a library of specially devised application functions as test building blocks, followed by a genetic evolutionary test generator to compose these application functions into effective test programs. |
Description: | Copyright © 2008 IEEE |
DOI: | 10.1109/DELTA.2008.31 |
Grant ID: | http://purl.org/au-research/grants/arc/LP0454838 |
Published version: | http://www2.computer.org/portal/web/csdl/doi/10.1109/DELTA.2008.31 |
Appears in Collections: | Aurora harvest Electrical and Electronic Engineering publications |
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hdl_49685.pdf | 359.56 kB | Publisher's PDF | View/Open |
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