Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/60040
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Type: Journal article
Title: Modeling interrupts for software-based system-on-chip verification
Author: Xu, X.
Lim, C.
Citation: IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 2010; 29(6):993-997
Publisher: IEEE-Inst Electrical Electronics Engineers Inc
Issue Date: 2010
ISSN: 0278-0070
1937-4151
Statement of
Responsibility: 
Xiaoxi Xu and Cheng-Chew Lim
Abstract: The interrupt mechanism in a system-on-chip (SoC) joins the SoCs hardware and software behaviors. We model interrupts as logical rather than physical events and accordingly provides guidelines to compose software components including interrupt-service-routines. As a benefit, classical indeterministic behaviors (due to the parallelism) in the software domain, such as preemption and nesting, can be constructed as early as raw hardware components are being integrated. In effect, while the interrupt mechanism itself is under rigorous stress, it is simultaneously driving the exercise of the entire SoC. This effect can be observed through software profiling at the hardware integration stage.
Keywords: Hardware-software co-verification
interrupt
parallelism
verification
Rights: Copyright 2010 IEEE
DOI: 10.1109/TCAD.2010.2043873
Appears in Collections:Aurora harvest 5
Electrical and Electronic Engineering publications

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