Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/60040
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dc.contributor.authorXu, X.-
dc.contributor.authorLim, C.-
dc.date.issued2010-
dc.identifier.citationIEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems, 2010; 29(6):993-997-
dc.identifier.issn0278-0070-
dc.identifier.issn1937-4151-
dc.identifier.urihttp://hdl.handle.net/2440/60040-
dc.description.abstractThe interrupt mechanism in a system-on-chip (SoC) joins the SoCs hardware and software behaviors. We model interrupts as logical rather than physical events and accordingly provides guidelines to compose software components including interrupt-service-routines. As a benefit, classical indeterministic behaviors (due to the parallelism) in the software domain, such as preemption and nesting, can be constructed as early as raw hardware components are being integrated. In effect, while the interrupt mechanism itself is under rigorous stress, it is simultaneously driving the exercise of the entire SoC. This effect can be observed through software profiling at the hardware integration stage.-
dc.description.statementofresponsibilityXiaoxi Xu and Cheng-Chew Lim-
dc.language.isoen-
dc.publisherIEEE-Inst Electrical Electronics Engineers Inc-
dc.rightsCopyright 2010 IEEE-
dc.source.urihttp://dx.doi.org/10.1109/tcad.2010.2043873-
dc.subjectHardware-software co-verification-
dc.subjectinterrupt-
dc.subjectparallelism-
dc.subjectverification-
dc.titleModeling interrupts for software-based system-on-chip verification-
dc.typeJournal article-
dc.identifier.doi10.1109/TCAD.2010.2043873-
pubs.publication-statusPublished-
dc.identifier.orcidLim, C. [0000-0002-2463-9760]-
Appears in Collections:Aurora harvest 5
Electrical and Electronic Engineering publications

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