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|Title:||A phase-locked loop reference spur modelling using Simulink|
|Citation:||Proceedings of the International Conference on Electronic Devices, Systems and Applications (ICEDSA 2010), held in Kuala Lumpur, Malaysia 2010: pp.279-283.|
|Conference Name:||International Conference on Electronic Devices, Systems and Applications (2010 : Kuala Lumpur, Malaysia)|
|Noorfazila Kamal, Said Al-Sarawi, Neil H. E. Weste and Derek Abbott|
|Abstract:||Phase-Locked Loops (PLLs) are a commonly used module in frequency synthesizers as part of RF transceivers. Simulating these modules is very time consuming. Therefore, a number of approaches to evaluate the performance of these modules through high level behavioural modelling are developed, where the focus is on the random noise aspect of these modules. In this paper, we introduce charge pump and Phase/Frequency Detector (PFD) non-idealities in the integer-N PLL behavioural model to estimate the periodic noise, which is also known as reference spurs. In addition, the effect of the VCO gain, loop filter order and loop bandwidth on the reference spurs level are taken into consideration. The proposed model was implemented in Simulink and showed less than ±3% error when compared to transistor level simulations from Cadence Spectre. Using this approach a 10 time improvement in simulation speed was achieved compared to transient analysis from Cadence Spectre.|
|Rights:||Copyright 2010 IEEE|
|Appears in Collections:||Aurora harvest 5|
Electrical and Electronic Engineering publications
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