Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/63409
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Type: Conference paper
Title: An event-assisted sequencer to accelerate matrix algorithms
Author: Burdeniuk, A.
To, K.
Lim, C.
Liebelt, M.
Citation: Proceedings of the IEEE 5th International Worthshop on Electronic Design, Test and Application (DELTA), held in Ho Chi Minh City, Vietnam, 13-15 Jan 2010: pp. 158-163
Publisher: IEEE
Publisher Place: USA
Issue Date: 2010
ISBN: 9780769539782
Conference Name: IEEE International Workshop on Electronic Design, Test and Applications (5th : 2010 : Vietnam)
Statement of
Responsibility: 
Adam Burdeniuk, Kiet N. To, Cheng Chew Lim and Mike J. Liebelt
Abstract: This paper presents a sequencer that accelerates matrix algorithms arising naturally in many multimedia and signal processing applications. The accelerator has been designed to carry out data management tasks common to these algorithms. A novel event-based parameter update mechanism allows production of continuously varying patterns to access triangular, banded and other irregular matrix structures. It has been verified that the accelerator significantly reduces the workload of the attached CPU for a wide range of algorithms. The accelerator has been implemented on a Virtex-5 FPGA platform where it required 1856 slices and achieved a post place-and-route speed of 64 MHz.
Keywords: Matrix
acceleration
sequencing
macroinstructions
event mechanism
Rights: © 2010 IEEE
DOI: 10.1109/DELTA.2010.12
Published version: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5438527
Appears in Collections:Aurora harvest
Electrical and Electronic Engineering publications
Environment Institute publications

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