Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/69833
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Type: Journal article
Title: Memristor MOS Content Addressable Memory (MCAM): Hybrid architecture for future high performance search engines
Author: Eshraghian, K.
Cho, K.R.
Kavehei, O.
Kang, S.
Abbott, D.
Kang, S.M.
Citation: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2011; 19(8):1407-1417
Publisher: IEEE-Inst Electrical Electronics Engineers Inc
Issue Date: 2011
ISSN: 1063-8210
1557-9999
Statement of
Responsibility: 
Kamran Eshraghian, Kyoung-Rok Cho, Omid Kavehei, Soon-Ku Kang, Derek Abbott and Sung-Mo Steve Kang
Abstract: Large-capacity content addressable memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore's Law for a few more years. This paper provides a new approach towards the design and modeling of Memory resistor (Memristor)-based CAM (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures.
Keywords: Content addressable memory (CAM); memory; memory resistor-based CAM (MCAM); memory resistor (memristor)-MOS hybrid architecture; modeling.
Rights: © 2010 IEEE
RMID: 0020112389
DOI: 10.1109/TVLSI.2010.2049867
Appears in Collections:Electrical and Electronic Engineering publications

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