Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/71514
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Type: Journal article
Title: An Analytical Approach for Memristive Nanoarchitectures
Author: Kavehei, O.
Al-Sarawi, S.
Cho, K.R.
Eshraghian, K.
Abbott, D.
Citation: IEEE Transactions on Nanotechnology, 2012; 11(0002):374-385
Publisher: IEEE
Issue Date: 2012
ISSN: 1536-125X
1941-0085
Statement of
Responsibility: 
Omid Kavehei, Said Al-Sarawi, Kyoung-Rok Cho, Kamran Eshraghian and Derek Abbott
Abstract: As conventional memory technologies are challenged by their technological physical limits, emerging technologies driven by novel materials are becoming an attractive option for future memory architectures. Among these technologies, Resistive Memories (ReRAM) created new possibilities because of their nanofeatures and unique I-V characteristics. One particular problem that limits the maximum array size is interference from neighboring cells due to sneak-path currents. A possible device level solution to address this issue is to implement a memory array using complementary resistive switches (CRS). Although the storage mechanism for a CRS is fundamentally different from what has been reported for memristors (low and high resistances), a CRS is simply formed by two series bipolar memristors with opposing polarities. In this paper, our intention is to introduce modeling principles that have been previously verified through measurements and extend the simulation principles based on memristors to CRS devices and, hence, provide an analytical approach to the design of a CRS array. The presented approach creates the necessary design methodology platform that will assist designers in implementation of CRS devices in future systems.
Keywords: Complementary resistive switch; memistive device; memory; memristor; nanoarchitectures; resistive RAM
Rights: © 2011 IEEE
RMID: 0020117949
DOI: 10.1109/TNANO.2011.2174802
Appears in Collections:Electrical and Electronic Engineering publications

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