Please use this identifier to cite or link to this item: https://hdl.handle.net/2440/77008
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Type: Conference paper
Title: Is there a smarter way to use 100 billion transistors?
Author: Li, F.
Khan, M.
Liebelt, M.
Ng, B.
Phillips, B.
Citation: Conference record of the 46th Asilomar Conference on Signals, Systems, and Computers, held in California on 4-7 November, 2012 / M.B. Matthews (ed.): pp.619-620
Publisher: IEEE
Publisher Place: USA
Issue Date: 2012
Series/Report no.: Conference Record of the Asilomar Conference on Signals Systems and Computers
ISBN: 9781467350501
ISSN: 1058-6393
Conference Name: Asilomar Conference on Signals, Systems & Computers (46th : 2012 : Pacific Grove, California)
Editor: Matthews, M.B.
Statement of
Responsibility: 
Francis Li, Muhammad Usman Khan, Michael Liebelt, Brian Ng and Braden Phillips
Abstract: Within the next decade it will be possible to build chip multiprocessors with thousands of cores. We can expect such devices to be exceptionally good at the kinds of problems massively parallel computers are already good at. That leaves a large class of interesting problems, especially those of artificial intelligence, for which multi-core processors are less well suited. Are there alternative architectures, scalable to 100 billion transistors and beyond, tolerant to device faults and process variations, and more appropriate for artificial intelligence problems than thousands of cores connected by a network on chip?
Rights: © 2012 IEEE
DOI: 10.1109/ACSSC.2012.6489082
Appears in Collections:Aurora harvest 4
Electrical and Electronic Engineering publications
Environment Institute publications

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