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|Title:||A new compact analog VLSI model for spike timing dependent plasticity|
|Citation:||Proceedings of the IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC, 2013 / M. Margala, R. Reis, A. Orailoglu, L. Carro, L. M. Silveira, H. F. Ugurdag (eds.), pp.7-12|
|Conference Name:||International Conference on Very Large Scale Integration (2013 : Istanbul)|
|Mostafa Rahimi Azghadi, Said Al-Sarawi, Nicolangelo Iannella, and Derek Abbott|
|Abstract:||Spike Timing Dependent Plasticity (STDP) is a time-based synaptic plasticity rule that has generated significant interest in the area of neuromorphic engineering and Very Large Scale Integration (VLSI) circuit design. During the last decade, STDP and STDP-like learning mechanisms have shown promising solutions for various real world applications, ranging from pattern recognition to robotics. This paper presents a novel analog VLSI model for STDP that possesses advantages compared to previously published VLSI STDP designs. The presented STDP circuit is capable of reproducing the outcomes of several well known experiments using various plasticity rules inducing STDP protocols that utilise pairs, triplets, and quadruplets of spike patterns. When the circuit is compared to state-of-the-art VLSI STDP circuits, it shows a compact and symmetric design that makes the proposed circuit a powerful component for use in designing STDP or time-based Hebbian learning experiments and applications.|
|Rights:||© 2013 IEEE|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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