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|Title:||Design and implementation of a GaAs systolic floating-point processing element|
|Citation:||IEE Proceedings Computers and Digital Techniques, 1996; 143(5):325-330|
|A. Beaumont-Smith, W. Marwood, C.C. Lim, K. Eshraghian|
|Abstract:||The design and layout of a prototype single precision systolic floating-point processing element (PE) is described. It is intended for use in a class of systolic array processors which perform matrix computations. Each PE is constructed from a digit-serial systolic ring of four programmable cells and performs floating-point multiplication and accumulation. A single PE has been fabricated in a 0.8 μm gallium arsenide E/D MESFET process and has a maximum clock speed of 300 MHz. The chip can be configured into a 16×16 array to achieve a peak computation rate of 2.5 GFLOPS.|
|Keywords:||Systolic arrays; Processing elements; GaAs devices|
|Rights:||© IEE, 1996|
|Appears in Collections:||Aurora harvest 7|
Electrical and Electronic Engineering publications
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