Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/86567
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Type: Journal article
Title: Spike-based synaptic plasticity in silicon: design, implementation, application, and challenges
Author: Rahimiazghadi, S.
Iannella, N.
Al-Sarawi, S.
Indiveri, G.
Abbott, D.
Citation: Proceedings of the IEEE, 2014; 102(5):717-737
Publisher: IEEE
Issue Date: 2014
ISSN: 0018-9219
1558-2256
Statement of
Responsibility: 
Mostafa Rahimi Azghadi, Nicolangelo Iannella, Said F. Al-Sarawi, Giacomo Indiveri, and Derek Abbott
Abstract: The ability to carry out signal processing, classification, recognition, and computation in artificial spiking neural networks (SNNs) is mediated by their synapses. In particular, through activity-dependent alteration of their efficacies, synapses play a fundamental role in learning. The mathematical prescriptions under which synapses modify their weights are termed synaptic plasticity rules. These learning rules can be based on abstract computational neuroscience models or on detailed biophysical ones. As these rules are being proposed and developed by experimental and computational neuroscientists, engineers strive to design and implement them in silicon and en masse in order to employ them in complex real-world applications. In this paper, we describe analog very large-scale integration (VLSI) circuit implementations of multiple synaptic plasticity rules, ranging from phenomenological ones (e.g., based on spike timing, mean firing rates, or both) to biophysically realistic ones (e.g., calcium-dependent models). We discuss the application domains, weaknesses, and strengths of various representative approaches proposed in the literature, and provide insight into the challenges that engineers face when designing and implementing synaptic plasticity rules in VLSI technology for utilizing them in real-world applications.
Keywords: Analog/digital synapse; Bienenstock–Cooper–Munro (BCM); calcium-based plasticity; learning; local correlation plasticity (LCP); neuromorphic engineering; rate-based plasticity; spike-based plasticity; spike-timing-dependent plasticity (STDP); spiking neural networks; synaptic plasticity; triplet STDP; very large-scale integration (VLSI); voltage-based STDP
Rights: © 2014 IEEE
RMID: 0020138282
DOI: 10.1109/JPROC.2014.2314454
Grant ID: http://purl.org/au-research/grants/arc/FT120100351
Appears in Collections:Electrical and Electronic Engineering publications

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