Positioning test-benches and test-programs in interaction-oriented system-on-chip verification
Date
2008
Authors
Xu, X.
Lim, C.
Liebelt, M.
Editors
Varma, P.
Advisors
Journal Title
Journal ISSN
Volume Title
Type:
Conference paper
Citation
Proceedings of IEEE International High Level Design Validation and Test Workshop, 19-21 November, 2008:pp.3-10
Statement of Responsibility
Conference Name
HLDVT '08 (2008 : Nevada, USA)
Abstract
In simulation-based system-on-chip (SoC) verification, in addition to the testbench (TB) - the basic facility for stimulation and observation, software native to the SoC also plays a part in interacting with the SoC. This software is referred to as the test-program (TP). However, the relationship between the TB, the TP and the SoC is not always intuitive and can cause conceptual confusion. This paper discusses this confusion and shows how to address it by positioning the TB and the TP naturally in the verification framework.