An Automated Design Methodology for FPGA-based Multi-Gbps LDPC Decoders
Date
2012
Authors
Pham, M.D.
Aziz, S.M.
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Conference paper
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2012 15th International Conference on Computer and Information Technology (ICCIT), 2012, pp.495-499
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15th International Conference on Computer and Information Technology (22 Dec 2012 - 24 Dec 2012 : Chittagong, Bangladesh)
Abstract
Low density parity check (LDPC) codes are errorcorrecting codes that offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware for fast processing to meet the real-time needs of communication systems. However hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming task. This paper presents an efficient automated high level approach to designing LDPC decoders using a collection of high level modelling tools. High data rate Multi-Gbps LDPC decoders have been developed and implemented on FPGA using the proposed methodology. These Multi-Gbps LDPC decoders can be utilized in the latest generation of high data rate wireless communication such as WLAN, WiMAX and DVB-S2.
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Copyright 2012 IEEE