Fault characterisation of complementary pass-transistor logic circuits
Date
2000
Authors
Aziz, S.M.
Karim, M.
Rashid, H.
Editors
Shaari, S.
Majlis, B.Y.
Majlis, B.Y.
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Conference paper
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ICSE 2000 : Proceedings of 2000 IEEE international conference on semiconductor electronics, 2000 / Shaari, S., Majlis, B.Y. (ed./s), pp.80-84
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4th IEEE International Conference on Semiconductor Electronics (ICSE2000) (13 Nov 1900 - 15 Nov 1900 : Guoman, Malaysia)
Abstract
Complementary Pass-transistor Logic (CPL) circuits result in speed improvement and power reduction compared to conventional static CMOS logic. The behaviour of this logic family under fault has not yet been studied. This paper presents the results of investigation into the behaviour of CPL circuits under various single faults. It is shown that all single transistor stuck-on faults are only detectable by IDDQ testing while all single stuck-open faults are only detectable by logic monitoring. Majority of the single bridging faults between the gate and source/drain terminals of the MOS transistors can be detected by current monitoring while a few are undetectable. © 2000 IEEE.
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Copyright IEEE 2000