Is there a smarter way to use 100 billion transistors?
Date
2012
Authors
Li, F.
Khan, M.
Liebelt, M.
Ng, B.
Phillips, B.
Editors
Matthews, M.B.
Advisors
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Volume Title
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Conference paper
Citation
Conference record of the 46th Asilomar Conference on Signals, Systems, and Computers, held in California on 4-7 November, 2012 / M.B. Matthews (ed.): pp.619-620
Statement of Responsibility
Francis Li, Muhammad Usman Khan, Michael Liebelt, Brian Ng and Braden Phillips
Conference Name
Asilomar Conference on Signals, Systems & Computers (46th : 2012 : Pacific Grove, California)
Abstract
Within the next decade it will be possible to build chip multiprocessors with thousands of cores. We can expect such devices to be exceptionally good at the kinds of problems massively parallel computers are already good at. That leaves a large class of interesting problems, especially those of artificial intelligence, for which multi-core processors are less well suited. Are there alternative architectures, scalable to 100 billion transistors and beyond, tolerant to device faults and process variations, and more appropriate for artificial intelligence problems than thousands of cores connected by a network on chip?
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© 2012 IEEE