Wafer-scale fabrication of ultra-thin silicon nanowire devices
Date
2013
Authors
Tran, P.D.
Wolfrum, B.
Stockmann, R.
Offenhausser, A.
Thierry, B.
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Conference paper
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Proceedings of the ... IEEE Conference on Nanotechnology / co-sponsored by IEEE Robotics and Automation Society (RAS) ... [et al.]. IEEE Conference on Nanotechnology, 2013, pp.405-409
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2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013) (5 Aug 2013 - 8 Aug 2013 : Beijing, China)
Abstract
We present a robust wafer-scale top-down process for the fabrication of locally thinned-downed silicon nanowire (SiNW) devices. The fabrication is based on electron-beam lithography in combination with a two-step tetramethylammonium hydroxide (TMAH) wet etch. We optimized the etching profile of the TMAH process on siliconon- insulator <100> using isopropanol additive and temperature regulation, yielding very low and controllable etching rates and enabling the formation of ultra-smooth silicon morphology. The optimized TMAH etching process was confined using photolithography to the middle sections of silicon nanowire channels to achieve localized step-etching of the nanowires. The thinned silicon nanowires were addressed via metal contact lines in the final step of the fabrication. Preliminary currentvoltage characterization in liquid demonstrated a p-channel field effect transistor behavior in depletion mode with a very high output current and negligible contact resistance. The proposed process provides an alternative route for reliable and reproducible fabrication of ultra-thin silicon nanowire devices.
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Copyright 2013 IEEE