Design and evaluation of a memory architecture for a parallel matrix processor array / Nicholas M. Betts.
Date
2000
Authors
Betts, Nicholas M.
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Thesis
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Abstract
Proposes a specialized matrix processor architecture that targets numerically intensive algorithms that can be cast in matrix terms.
School/Discipline
Dept. of Electrical and Electronic Engineering
Advisory Centre for University Education
Advisory Centre for University Education
Dissertation Note
Thesis (Ph.D.) - -University of Adelaide, Dept. of Electrical and Electronic Engineering, 2000
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Description
CD-ROM in pocket on back end paper.
Bibliography: leaves 254-259.
xiv, 259 leaves : ill. ; 30 cm + 1 computer optical disc (4 3/4 in.)
Bibliography: leaves 254-259.
xiv, 259 leaves : ill. ; 30 cm + 1 computer optical disc (4 3/4 in.)