Phillips, B.Kelly, D.Ng, B.Luk, F.2007-07-102007-07-102006Advanced Signal Processing Algorithms, Architectures, and Implementations XVI / F.T. Luk (ed.) pp. 631302 1-9 [electronic resource]0-8194-6392-20277-786X1996-756Xhttp://hdl.handle.net/2440/35217Copyright 2006 Society of Photo-Optical Instrumentation Engineers.Low density parity check decoders use computation nodes with multioperand adders on their critical path. This paper describes the design of estimating multioperand adders to reduce the latency, power and area of these nodes. The new estimating adders occasionally produce inaccurate results. The effect of these errors and the subsequent trade-off between latency and decoder frame error rate is examined. For the decoder investigated it is found that the estimating adders do not degrade the frame error rate.enConference paper002006219410.1117/12.6801990002419471000022-s2.0-3375058440451777Phillips, B. [0000-0001-8288-4791]Ng, B. [0000-0002-8316-4996]