Xu, X.Lim, C.Mir, S.Micheli, G.Reis, R.Simeu, E.2007-07-102007-07-102006Proceedings of the IFIP International Conference on Very Large Scale Integration, Nice, France, 2006 : pp. 98-1033901882197978-3-901882-19-7http://hdl.handle.net/2440/35218This paper presents a novel modelling methodology for system-on-chip (SoC) verification based on software techniques. This methodology facilitates the automation of test generation; it also enables the focuses being placed on system-level behaviors such as concurrency and resource-contentions. We have demonstrated the feasibility to generalize heterogeneous interactions systematically and use them as the building blocks to generate complex test-cases of real-world concurrency.en© Copyright 2006 IEEEConference paper002006219510.1109/VLSISOC.2006.3132110002435239000182-s2.0-4584908940351776Lim, C. [0000-0002-2463-9760]