Kelly, D.Phillips, B.Al-Sarawi, S.Marco Mattavelli,2011-06-142011-06-142009Proceedings of the 2009 Conference on Design & Architectures For Signal And Image Processing / M. Mattavelli (ed.): pp.97-104http://hdl.handle.net/2440/64509Arithmetic data value speculation increases the throughput of a processor pipeline by speculatively issuing the dependent operations of an arithmetic operation based on the early arrival of an approximate result. Suitable approximate multipliers calculate a product faster than an exact multiplier, with an associated probability that the approximate product is correct. This paper presents the design of a family of signed approximate multipliers for use in a speculative data path. A signed 32x32 bit multiplier synthesised with the TSMC Artisan 180nm SAGE-X™ cell library is found to be 20% faster than a full-adder based tree multiplier, with a probability of error less than 14% for benchmark applications.enCopyright status unknownConference paper002010593430944Phillips, B. [0000-0001-8288-4791]Al-Sarawi, S. [0000-0002-3242-8197]