Piyaratna, S.Duong, N.Carr, J.Bird, D.Kennedy, S.Udina, A.Jenkinson, P.2015-03-222015-03-2220132013 International Conference on Radar - Beyond Orthodoxy: New Paradigms in Radar, RADAR 2013, 2013, pp.554-5599781467351775http://hdl.handle.net/2440/90088This paper presents the design of the Digital RF Processing (DRFP) system for generating many of the RF effects within the Advanced Radar Environment Simulator (ARES) Hardware-in-the-Loop system developed within the Hardware-in-the-Loop Technology and Simulation Group (HTS) of Weapons Systems Division (WSD), DSTO. This system is based on Digital RF Memory (DRFM) technology. The DRFM signal processing is performed on a digitised signal on a commercial-off-the-shelf (COTS) Field Programmable Gate Array (FPGA) hardware board. The RF Up/Down conversion is performed by a COTS RF module. The RF up/down converter translates an 800MHz instantaneous band in range 2-18 GHz down to 500 MHz IF signal (100 - 900 MHz). The ARES Digital RF Processor (DRFP) provides the technique designer with a set of tools to model a number of environmental effects, such as Doppler, Range Delay, intra-pulse complex modulations, and multi-point convolutions. The ARES DRFP provides a real-time communication link to receive high fidelity generic environmental parameters which are computed by a numerical model of the radar environment. This feature provides the technique designer with significant flexibility compared to other typical Radar/RF scene generators. This paper discusses the implementation details and the design strategies of the development. Preliminary results of the ARES DRFP output are also discussed.en© 2013 Commonwealth of AustraliaDigital RF Memory (DRFM); Field Programmable Gate Array (FPGA); Hardware-in-the-Loop (HWILConference paper003001367210.1109/RADAR.2013.66520482-s2.0-8489113230378162