Xu, X.Lim, C.Lim, Y.2007-07-102007-07-102006IEEE Asia Pacific Conference on Circuits and Systems, 4-7 Dec, 2006:pp.836-8391424403871978-1-4244-0386-8http://hdl.handle.net/2440/35215Copyright © 2006 IEEESystem-on-chip (SoC) design paradigm makes design verification a more time-consuming task. Therefore, for simulation-based methods, test quality is extremely important. This paper presents a method that increases the test quality by exploiting the concurrency in a system. The main idea is to generalize the elements of concurrency as transfers and then transform the system into a transfer-resource-graph. The graph can be traversed to produce high-quality tests. To further optimize the test quality in terms of concurrency, we are able to generate event-driven test-programs.enExploiting concurrency in system-on-chip verificationConference paper002006219110.1109/APCCAS.2006.3421510002467932002092-s2.0-4584912196251780Lim, C. [0000-0002-2463-9760]