Tabrizi, Nozar2006-12-282006-12-2819971997http://hdl.handle.net/2440/19119Bibliography: leaves 158-167.xvii, 173 leaves ; 30 cm.Investigates two level logic synthesis of asynchronous circuits from signal transition graphs (STGs) under the inertial gate delay model and the well behaved environment. Focuses on design methodologies and hazard free implementations based on redundant logic where the inertial delay model does not help to avoid hazards.189457 bytesapplication/pdfenAutomatic control.Asynchronous circuits Design and construction.Delay lines.Thesis