Please use this identifier to cite or link to this item: http://hdl.handle.net/2440/2435
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Type: Journal article
Title: A-DELTA: A 64-bit high speed, compact, hybrid dynamic-CMOS/threshold-logic adder
Author: Celinski, P.
Cotofana, S.
Abbott, D.
Citation: Lecture Notes in Computer Science/Lecture Notes in Artificial Intelligence, 2003; 2687:73-80
Publisher: Springer-Verlag Berlin
Issue Date: 2003
ISSN: 0302-9743
1611-3349
Statement of
Responsibility: 
Peter Celinski, Sorin D. Cotofana and Derek Abbott
Abstract: A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 pm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.
Description: The original publication is available at www.springerlink.com
RMID: 0020032173
DOI: 10.1007/3-540-44869-1_10
Appears in Collections:Electrical and Electronic Engineering publications

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