Please use this identifier to cite or link to this item:
|Scopus||Web of Science®||Altmetric|
|Title:||A-DELTA: A 64-bit high speed, compact, hybrid dynamic-CMOS/threshold-logic adder|
|Citation:||Lecture Notes in Computer Science/Lecture Notes in Artificial Intelligence, 2003; 2687:73-80|
|Peter Celinski, Sorin D. Cotofana and Derek Abbott|
|Abstract:||A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 pm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.|
|Description:||The original publication is available at www.springerlink.com|
|Appears in Collections:||Electrical and Electronic Engineering publications|
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.