Please use this identifier to cite or link to this item:
https://hdl.handle.net/2440/2435
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Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Celinski, P. | - |
dc.contributor.author | Cotofana, S. | - |
dc.contributor.author | Abbott, D. | - |
dc.contributor.editor | Mira, J. | - |
dc.contributor.editor | Alvarez, J.R. | - |
dc.date.issued | 2003 | - |
dc.identifier.citation | Lecture Notes in Artificial Intelligence, 2003; 2687:73-80 | - |
dc.identifier.issn | 0302-9743 | - |
dc.identifier.issn | 1611-3349 | - |
dc.identifier.uri | http://hdl.handle.net/2440/2435 | - |
dc.description | The original publication is available at www.springerlink.com | - |
dc.description.abstract | A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 pm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders. | - |
dc.description.statementofresponsibility | Peter Celinski, Sorin D. Cotofana and Derek Abbott | - |
dc.language.iso | en | - |
dc.publisher | Springer-Verlag Berlin | - |
dc.source.uri | http://dx.doi.org/10.1007/3-540-44869-1_10 | - |
dc.title | A-DELTA: A 64-bit high speed, compact, hybrid dynamic-CMOS/threshold-logic adder | - |
dc.type | Journal article | - |
dc.identifier.doi | 10.1007/3-540-44869-1_10 | - |
pubs.publication-status | Published | - |
dc.identifier.orcid | Abbott, D. [0000-0002-0945-2674] | - |
Appears in Collections: | Aurora harvest 2 Electrical and Electronic Engineering publications |
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