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|Title:||Threshold logic parallel counters for 32-bit multipliers|
|Citation:||Smart structures, devices, and systems : 16-18 December 2002, Melbourne, Australia / Erol C. Harvey, Derek Abbott, Vijay K. Varadan (eds.), pp. 205-214|
|Series/Report no.:||Proceedings of SPIE--the International Society for Optical Engineering ; 4935|
|Conference Name:||International Symposium on Smart Materials, Nano- and Micro-Smart Systems (2002 : Melbourne, Australia)|
|Peter Celinski, Sorin D. Cotofana, and Derek Abbott|
|Abstract:||In recent years, there has been renewed interest in Threshold Logic (TL), mainly as a result of the development of a number of successful implementations of TL gates in silicon. Threshold Logic enables, in some instances, the design of digital integrated circuits with a significantly reduced transistor count and area. This paper addresses the important problem of designing technologically feasible parallel (m,n) counters for using TL for binary multiplication. A number of counter design techniques are reviewed and some novel parallel counter designs are presented that allow the design of area efficient 32-bit multiplier partial product reduction circuits.|
|Description:||© 2003 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.|
|Appears in Collections:||Electrical and Electronic Engineering publications|
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