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dc.contributor.authorXu, X.-
dc.contributor.authorLim, C.-
dc.contributor.editorMir, S.-
dc.contributor.editorMicheli, G.-
dc.contributor.editorReis, R.-
dc.contributor.editorSimeu, E.-
dc.identifier.citationProceedings of the IFIP International Conference on Very Large Scale Integration, Nice, France, 2006 : pp. 98-103-
dc.description.abstractThis paper presents a novel modelling methodology for system-on-chip (SoC) verification based on software techniques. This methodology facilitates the automation of test generation; it also enables the focuses being placed on system-level behaviors such as concurrency and resource-contentions. We have demonstrated the feasibility to generalize heterogeneous interactions systematically and use them as the building blocks to generate complex test-cases of real-world concurrency.-
dc.description.statementofresponsibilityJustin Xu ; Cheng-Chew Lim-
dc.publisherInternational Federation for Information Processing-
dc.rights© Copyright 2006 IEEE-
dc.titleModelling heterogeneous interactions in SoC verification-
dc.typeConference paper-
dc.contributor.conferenceIFIP International Conference on Very Large Scale Integration (2006 : Nice, France)-
dc.identifier.orcidLim, C. [0000-0002-2463-9760]-
Appears in Collections:Aurora harvest 6
Electrical and Electronic Engineering publications

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